Abstract—An improved chip identification (ID) generator,otherwise known as a physically unclonable function (PUF) is described. Similar to previous designs, a cell, i, is used to obtain a measure of the difference in period of four ring oscillators and obtain the residue Ri, a random variable. Experiments show it is normally distributed with a mean of 0. A binary output value of 0 or 1 assigned depending on the sign of Ri. When |E(Ri)| is large, this scheme consistently gives the same output.
Unfortunately, when it is small, the repeatability is compromised,
particularly when variations in operating conditions such as supply voltage and temperature are also taken into account, which is a common problem for all previous works. To address this problem, we propose a cell with configurable ring oscillators together with an orthogonal re-initialisation scheme. Together,these two techniques maximise repeatability by causing the distribution of the mean of different Ri’s to change from normal to bimodal. We implement this design in the Xilinx Spartan- 3e FPGA. Nine FPGA chips are tested, and experimental results show that the new method significantly enhances reliability of ID generation and tolerance to environmental changes. Bit flip rate is reduced from 1.5% to approximately 0 at a fixed supply voltage and room temperature. Over the 20 − 80 ◦C temperature range, and a 25% variation in supply voltage, the bit flip rate is reduced from 1.56% to 3.125 × 10 −7, which is a 50000× improvement.
Unfortunately, when it is small, the repeatability is compromised,
particularly when variations in operating conditions such as supply voltage and temperature are also taken into account, which is a common problem for all previous works. To address this problem, we propose a cell with configurable ring oscillators together with an orthogonal re-initialisation scheme. Together,these two techniques maximise repeatability by causing the distribution of the mean of different Ri’s to change from normal to bimodal. We implement this design in the Xilinx Spartan- 3e FPGA. Nine FPGA chips are tested, and experimental results show that the new method significantly enhances reliability of ID generation and tolerance to environmental changes. Bit flip rate is reduced from 1.5% to approximately 0 at a fixed supply voltage and room temperature. Over the 20 − 80 ◦C temperature range, and a 25% variation in supply voltage, the bit flip rate is reduced from 1.56% to 3.125 × 10 −7, which is a 50000× improvement.
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