Abstract—The design mainly discussed the low powerconsumption cymometer’s circuit implementation plan. It isbased on the most practical digital system simulation VHDL language. Then through compilation, simulation, downloadedto the FPGA device up with MAX+PLUS software,investigated cymometer’s practicable. And through the use of electronic circuit simulation EWB software verified cymometer’s correct in theory.
Compare to the other cymometer ,it have a lot of advantages: It can measure the frequency of square wave signal, and show the frequency control with a digital display tube; By changing the program to reach the purpose of expanding measuring range;It also set up a range status display signal, when it excess the maximum range, it will alarm. But in addition to considering the cymometer’s small size, simple structure, high accuracy, well reliability and use convenient and so on, it’s low power consumption is a key in this design, and it incarnate this article’s significance.
Compare to the other cymometer ,it have a lot of advantages: It can measure the frequency of square wave signal, and show the frequency control with a digital display tube; By changing the program to reach the purpose of expanding measuring range;It also set up a range status display signal, when it excess the maximum range, it will alarm. But in addition to considering the cymometer’s small size, simple structure, high accuracy, well reliability and use convenient and so on, it’s low power consumption is a key in this design, and it incarnate this article’s significance.
Keywords-VHDL language ； Low power consumption ；
Digital cymoment；Alarm.
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